Present complementary metal oxide semiconductor (CMOS) dynamic random access memory (DRAM) circuits are frequently used for main memory in a variety of applications including desk top and portable computer systems. These dynamic random access memory circuits frequently utilize memory cells formed by a single access transistor and a storage capacitor for storing an electrical charge representing a datum. An increasing demand for greater speed and cell density in dynamic random access memory circuits has been partially satisfied by reducing the operating voltage and the feature sizes of the memory cell. This reduction in operating voltage reduces the total charge that must be transferred to active signal lines. The reduction in feature sizes decreases load capacitance of the signal lines. Large capacitance signal lines such as word lines, however, still require large drive transistors to satisfy speed requirements. Moreover, active word lines of memory circuits organized in banks must be latched. These latched active word lines permit activation of word lines in alternate banks without deactivation of the first bank.
Row decode circuits of the prior art have segmented word lines to reduce load capacitance of each drive circuit. The decode circuit of FIG. 6 of the prior art includes thirty-six word line segment drive circuits 650 for each global row decode circuit 600. In operation, global word line signal /WLGS of the global row decode circuit 600 is precharged high by transistor 611. The global row decode circuit is selected when address signals turn on transistors 615 and 619, and block select signal /BSEL2 is driven low. The resulting current path discharges terminal 613 and drives global word line signal /WLGS low at each of the thirty-six word line segment drive circuits 650. This low level is not latched, and must be maintained, therefore, by the active state of the address signals and the block select signals. The X+ drive circuit of FIG. 5 selects one of the word line segment drive circuits 650. This X+ drive circuit includes a decode circuit 500 for producing drive signal /X+ and a buffering inverter 550 for producing complementary signal X+. These drive signals together with a low level of global word line select signal /WLGS produce a high level output signal WLa at word line lead 639.
Previous memory circuits have employed row decode circuits with level translators as disclosed in U.S. Pat. Nos. 5,668,485, 5,808,482 and 5,696,721. The row decode circuit of U.S. Pat. No. 5,696,721 disclosed in FIG. 7, for example, uses a level translator to increase the word line voltage and avoid a threshold voltage loss at the storage capacitor due to the access transistor. The row decode circuit is activated when block select signal BS.sub.-- is driven low and address signals RFJ and RFK are driven high. The resulting low signal at the control gate of transistor 706 couples the control gate of transistor 712 to high voltage supply Vpp, thereby activating word line drive circuit 722. The decode circuit is reset when block select signal BS.sub.-- goes high. This high level turns off transistor 704 and turns on transistor 710. In this state, transistors 706 and 710 are both conducting. Transistor 706 must have a width-to-length ratio designed for rapid activation of drive circuit 722. Transistor 710 must have a width-to-length ratio, however, that is sufficient to overcome transistor 706 and turn off the decode circuit. This conflict between transistor 706 and 710 is illustrated by the simulated waveforms of FIG. 8. Therein, a width of transistor 710 is held at 2.0 .mu.m while the width of transistor 706 assumes widths of 0.8 .mu.m, 3.0 .mu.m and 6.0 .mu.m. Although a width of 6.0 .mu.m for transistor 706 might improve rise time of a word line in response to a low level of row address strobe signal RAS, the decode circuit fails to reset in response to the high level of row address strobe signal RAS. This failure to reset results in an intermediate state of the output signal and lost data along a word line that fails to turn off. A corresponding increase in the width of transistor 710 would have a disadvantage of requiring grater area for the decode circuit.